QUOTE:
Power-on hard reset
The NOT_RESET pin provides a power-on or hard reset function. It must be asserted (low)
before the clocks and power supply are stable. When the NOT_RESET pin is asserted
(regardless of any other inputs), all modules are asynchronously forced into their power on reset
state.
The NOT_RESET pin should only be de-asserted (high) after both of the following events have
taken place:
the clocks and power are stable, to guarantee well defined behavior,
the NOT_TRST TAP reset pin has been asserted.
When the NOT_RESET pin is de-asserted, the CPU enters its boot sequence. The sequence
starts only after the rising edge of the NOT_RESET pin is internally synchronized and the clocks
are stable.
Bootstrap code can either be in off-chip ROM or can be received through the DCU.
If I remember well, you are right. But the sequence between RESET and nRST is critical to respect if you want to put the CPU in STALL mode which is necessary to install a DCU trap. Both signals needs to be low together and one needs to be high before the other.
I remember having written something on that STALL mode in a forum.
But that forum is down for now.
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